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City Sunnyvale
City Sunnyvale
State/Province California [CA]
Country United States [US]
Title Principal ASIC Design Engineer (AMRD2037)
Req # AMRD2037
Job Status Full Time Regular
Functional Area R&D
Position Overview Responsibilities: · ASIC architecture research, analysis and specification
· High performance and high quality ASIC design from specification to RTL implementation;
· Perform ASIC verification, synthesis, timing analysis
· IP evaluation, verification and integration
· Back-end ASIC vendor support
· System/board level bring up, debugging and support,
Requirements: · Strong track record of ASIC design from concept to mass production;
· Hands-on experience on Verilog HDL and good at algorithms;
· Experience of high performance ASIC design from specification to system bring up;
· FPGA design experience to verify large scale ASIC
· Networking concept and protocols knowledge
· Highly motivated, positive, detail oriented and responsible;
· Good team player and good communication skills;
· Familiar with C programming is plus;
· 8 years or more networking or processor experience
Educational Requirement:
· Bachelors of Electrical Engineering or Bachelors of Civil Engineering
· Masters Science, Electrical Engineering preferred
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EEOC / AAP Accommodation: If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Fortinet, Inc at (408) 235-7700 of
[email protected] for assistance.
EEO: All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.
