Xilinx is seeking a talented, motivated and self-driven FPGA engineer to be part of the SDAccel platform IP development team. SDAccel is the next generation software programming environment under the SDx initiative to enable application developers with little or no FPGA expertise to use high level programming languages such as OpenCL, C and C to leverage the power of programmable hardware for application acceleration.
This high performance team is involved in development of a scalable, reconfigurable acceleration platform that can be optimized for machine learning, video transcoding, image and speech recognition, CloudRAN, and Big Data analytics applications. Candidate will get an opportunity to work on deployment of FPGAs with Tier1 Hyperscale cloud as well as other customers.
Responsibilities: - End-to-end system level design of the platform including hardware, board, shell design development. Responsibilities will also include integration of hardware, firmware and software and making sure they all work together.
- FPGA IP integration and testing, board and system hardware bring up of the shell used in acceleration applications in FPGA based PCIe cards
- Xilinx FPGA design, synthesis, speed and gate optimization, Verilog code development, test bench creation and validation of the design
- Hands-on work involving board bring-up, debugging and validating designs that use PCIe Gen3/4, high speed Ethernet networking, DDR3/ DDR4, AXI interconnect and other networking protocols.
- Define the requirements by working with software and firmware teams to implement complete system level solution
- Drive the planning, implementation, architecture and microarchitecture and verification of SDAccel platform features
Bachelor's Degree in Electrical Engineering; MSEE preferred
5+ years' experience in system level design
Verilog coding and integration, test set up, bench creation and debug
Demonstrated knowledge of FPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring up and testing
Knowledge of timing constraints ie Synopsys Design Constraints format.
Extensive past experience in FPGA IP integration and testing, board and system hardware bring up
Knowledge of networking protocols, interfaces and standards like PCIe Gen3/4 and 10G Ethernet
Knowledge of memory interfaces like DDR3, DDR4
Knowledge of AXI interconnect protocol
Knowledge of serial protocols like I2C, SPI, JTAG
Scripting experience with Tcl, which is the application programming interface for Vivado, and Perl/Python
Good communication and interpersonal skills
Ability to lead a team and coordinate with multiple other teams to drive projects to completion
